An integrated circuit (IC) can be considered to be a graph of connected primitives such as, but not limited to, transistors and resistors. Such an entity is commonly referred to as a netlist. Each primitive is mapped to one or more layout objects that are two-dimensional geometrical objects such as, but not limited to, rectangles, polygons, and paths. In turn, these layout objects are used to define regions within a semiconductor die, which will receive different processing steps such as dopant, implants to produce N-type or P-type regions during the integrated circuit fabrication process.
Ultimately, every netlist must be mapped to an IC design layout (“layout”) prior to its manufacture. IC designers typically use electronic design automation (“EDA”) applications to create a layout. These EDA applications provide sets of computer-based tools for creating, editing, and analyzing layouts.
EDA applications create layouts from a netlist by various operations. Some, but not all, of a physical design (“PD”) operations need to transform a netlist to a layout include: (1) placement which specifies locations of the IC components; (2) routing which generates layout objects to connect IC components; (3) additional operations to complete a layout such as, but not limited to adding substrate/well contacts and power/ground routing. The result of the physical design process is a layout.
A netlist can be partitioned into clusters of functional blocks (“blocks”) such as logic, memory, analog and other functions. Since interface specifications for interactions among blocks are usually well defined, different IC designers can create each block independently and concurrently. IC designers create these blocks by assembling pre-built design components (“components”) using EDA applications. These components are stored in a design component library (“DCL”) and contain pre-characterized data called views such as, but not limited to, layout, logic, timing, power and other data views, required by EDA applications.
FIG. 1 illustrates some embodiments of a physical design process 1010 for a block. The process starts at 1040 by accepting a block specification 1030 and selecting components from a pre-built Design Component Library 1020. At 1050, the process computes component locations (“placement”) and then generates the required component interconnections at 1060_(“routing”). The result is a block 1070 composed of placed and interconnected components.
FIG. 2 illustrates some embodiments of an IC logic block composed of placed and routed components which are called standard cells. A standard cell implements a basic logic function and is stored in a pre-built standard cell library. All cells in a standard cell library conform to a certain set of standard requirements, including physical dimensions, electrical characteristics, etc. The physical design process places standard cell components in a two-dimension plane representing an IC chip and then generates interconnection among them. Such a physical design flow is called an application specific integrated circuit (“ASIC”) flow. 210 is a representative standard cell component while 220 is a representative interconnection or routing among components.
FIG. 3 illustrates some embodiments of a physical design process 300 to generate an ASIC IC block. A standard cell library 310 contains basic design components, implemented as layout, logic, timing, power and other data views. Logic or physical synthesis tools 312, such as Synopsys Physical Compiler, transfer the logic description of the design 302 into a netlist 304 of logic views of cells; then placement tools 314, such as Cadence Encounter, transfer the netlist into a placed design in which cells are placed within a die area; then routing tools 316, such as Cadence Encounter, transfer a placed design to a IC mask layout 308 by generating required connections among cells. Both 314 and 316 use the layout view of the cells.
FIG. 4 illustrates some embodiments of an IC memory block composed of a bit-cell array and peripheral (“periphery”) blocks. 430 is a bit cell array which contains IC components providing the memory functionality. Periphery 410, 420 and 440 contain circuitry to read and write information to and from the bit cell array. Periphery 450 and 460 are so called dummies blocks required to be present during a manufacturing process. The design of the bit-cell array and individual bit cells uses very specialized techniques to ensure that these structures are manufacturable with smallest layout area and is beyond the scope of this document. Peripheries, however, are implemented in a similar fashion as a logic block flow. Bit slice components are placed and routed to form a particular periphery such as, but not limited to, an address decode block. These bit slice components are stored in a collection analogous to a standard cell library.
The construction of the memory peripheral block is done either manually by a human designer or by a specialized EDA tool called a memory compiler. The operation to create a periphery is similar to that of an ASIC flow. FIG. 5 illustrates some embodiments of a process 510 used to generate a memory block. The process at 524 computes a memory architecture required for the memory requirement 520. At 528 the process selects a periphery to generate. At 532 the process computes the periphery parameters based on the memory architecture determined in 524. At 536 the process selects a set of bit slice components, places them in 540, and generates interconnections at 544. At 548 the process determines if there are any additional peripheries to be generated. If there are additional peripheries to be generated, the process returns to 528 to select another periphery to generate. If there are no more peripheries to be generated, the process produces the memory block at 552.
The quality of the components used to create the IC blocks is the primary determinant of the final IC design quality. Therefore, significant amount of resources are invested in the optimization of the components. The optimization objectives for the creation of the components include such aspects, but are not limited to, layout area, timing, power and signal integrity.
Each component is typically optimized individually with the assumption that electrically isolated neighboring components will have limited impact on the component eventual performance. For example, physical IP vendors like ARM optimize standard cells without considering context dependencies. Normally several versions of cell libraries are made for each process node to accommodate special needs for power consumption, speed or other user requirement.
Similar efforts are undertaken to design components comprising various memory peripheral blocks. For example, many variants of bit slice components for an address decode block are created to accommodate different configuration of bit cell arrays that a decode block might connect to. These variants are necessary since different bit cell array configuration have different electrical characteristics that must be accommodated in a particular bit-cell array configuration to order to satisfy performance requirements. These pre-built components are then selected by either a memory designer or an EDA memory compiler tool to construct a particular variant of a memory block.
IC fabrication is an extremely complex manufacturing process. Numerous manufacturing related considerations such as, but not limited to, lithography, etch, deposition and chemical mechanical polishing affect the final quality of the manufactured IC. Traditionally IC designers have not had to consider the manufacturing considerations during the design process; however, starting at the 130 nm process node, manufacturing considerations have started to impact negatively fabricated IC circuit performance relative to design requirements.
The manufacturing yield of an IC is defined to be the percentage of manufactured ICs meeting the product requirements. Examples of product requirements include, but are not limited to, functional correct operations at the specified clock frequency range and power dissipation below a specified value. The manufacturing yield is impacted by such considerations, but is not limited to, as the inherent variations of the IC manufacturing process, the semiconductor electrical property variations due to proximity effects such as STI stress and orientation relative to intentionally introduced stress structures, lithographic context dependent printability, and localized chemical mechanical polish (CMP) effects.
It has been recognized that variants of integrated circuit components dependent on different manufacturing considerations could be provided to designers so that the tradeoffs regarding yield and circuit performance can be made. Current approaches provide yield component variants that are developed and characterized in isolation without regard to neighboring context. A neighboring context (“context”) is defined to be the surrounding layout regions of a particular component during fabrication as well as during a component's operational mode. Physical design tools using components characterized for yield without regard to the context may not improve the yield, and sometimes even reduces it.